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| DG408, DG409 Data Sheet June 1999 File Number 3283.5 Single 8-Channel/Differential 4-Channel, CMOS Analog Multiplexers The DG408 Single 8-Channel, and DG409 Differential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular DG508A and DG509A series devices. They each include an array of eight analog switches, a TTL/CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ENABLE input for device selection when several multiplexers are present. The DG408 and DG409 feature lower signal ON resistance (<100) and faster switch transition time (tTRANS < 250ns) compared to the DG508A or DG509A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG408 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from 5V to 20V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range. Features * ON Resistance (Max, 25oC). . . . . . . . . . . . . . . . . . . 100 * Low Power Consumption (PD) . . . . . . . . . . . . . . . <11mW * Fast Switching Action - tTRANS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <250ns - tON/OFF(EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . <150ns * Low Charge Injection * Upgrade from DG508A/DG509A * TTL, CMOS Compatible * Single or Split Supply Operation Applications * Data Acquisition Systems * Audio Switching Systems * Automatic Testers * Hi-Rel Systems * Sample and Hold Circuits * Communication Systems * Analog Selector Switch Pinouts DG408 (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER DG408DJ DG408DY DG409DJ DG409DY TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3 M16.15 E16.3 M16.15 A0 1 EN 2 V- 3 S1 4 S2 5 S3 6 S4 7 D8 16 A1 15 A2 14 GND 13 V+ 12 S5 11 S6 10 S7 9 S8 DG409 (PDIP, SOIC) TOP VIEW A0 1 EN 2 V- 3 S1A 4 S2A 5 S3A 6 S4A 7 DA 8 16 A1 15 GND 14 V+ 13 S1B 12 S2B 11 S3B 10 S4B 9 DB 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 DG408, DG409 Functional Block Diagrams DG408 DG409 S1 D S1A DA S2 DECODER/ DRIVER S4A S1B DECODER/ DRIVER DB S8 S4B 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT DIGITAL INPUT PROTECTION DIGITAL INPUT PROTECTION A0 A1 A2 EN A0 A1 EN TRUTH TABLE DG408 A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH NONE 1 2 3 4 5 6 7 8 A1 X 0 0 1 1 NOTES: A0 X 0 1 0 1 TRUTH TABLE DG409 EN 0 1 1 1 1 ON SWITCH NONE 1 2 3 4 1. VAH Logic "1" 2.4V. 2. VAL Logic "0" 0.8V. 2 DG408, DG409 Pin Descriptions - (DG408) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL A0 EN VS1 S2 S3 S4 D S8 S7 S6 S5 V+ GND A2 A1 DESCRIPTION Logic Decode Input (Bit 0, LSB) Enable Input Negative Power Supply Terminal Source (Input) for Channel 1 Source (Input) for Channel 2 Source (Input) for Channel 3 Source (Input) for Channel 4 Drain (Output) Source (Input) for Channel 8 Source (Input) for Channel 7 Source (Input) for Channel 6 Source (Input) for Channel 5 Positive Power Supply Terminal (Substrate) Ground Terminal (Logic Common) Logic Decode Input (Bit 2, MSB) Logic Decode Input (Bit 1) Pin Descriptions - (DG409) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL A0 EN VS1A S2A S3A S4A DA DB S4B S3B S2B S1B V+ GND A1 DESCRIPTION Logic Decode Input (Bit 0, LSB) Enable Input Negative Power Supply Terminal Source (Input) for Channel 1a Source (Input) for Channel 2a Source (Input) for Channel 3a Source (Input) for Channel 4a Drain a (Output a) Drain b (Output b) Source (Input) for Channel 4b Source (Input) for Channel 3b Source (Input) for Channel 2b Source (Input) for Channel 1b Positive Power Supply Terminal Ground Terminal (Logic Common) Logic Decode Input (Bit 1, MSB) 3 DG408, DG409 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V Digital Inputs, VS , VD (Note 3). . . . . .(V-) -2V to (V+) + 2V or 20mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA Thermal Information Thermal Resistance (Typical, Note 4) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 125oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on SX , DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 4. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER DYNAMIC CHARACTERISTICS Transition Time, tTRANS Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS (See Figure 1) (See Figure 3) (See Figure 2) Full 25 25 Full 10 - 160 115 105 20 -75 8 3 250 150 225 150 - ns ns ns ns ns pC dB pF pF Break-Before-Make Interval, tOPEN Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q OFF Isolation Logic Input Capacitance, CIN Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) DG408 DG409 Drain ON Capacitance, CD(ON) DG408 DG409 DIGITAL INPUT CHARACTERISTICS Logic Input Current, Input Voltage High, IAH Logic Input Current, Input Voltage Low, IAL ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) rDS(ON) Matching Between Channels, rDS(ON) Source OFF Leakage Current, IS(OFF) (See Figure 2) CL = 10nF, VS = 0V VEN = 0V, RL = 1k, f = 100kHz (Note 9) f = 1MHz VEN = 0V, VS = 0V, f = 1MHz VEN = 0V, VD = 0V, f = 1MHz Full 25 25 25 25 25 25 - 26 14 37 25 - pF pF pF pF A A VEN = 3V, VD = 0V, f = 1MHz, VA = 0V or 3V 25 25 VA = 2.4V, 15V VEN = 0V, 2.4V, VA = 0V Full Full -10 -10 - 10 10 Full VD = 10V, IS = -10mA (Note 7) VD = 10V, -10V (Note 8) VEN = 0V, VS = 10V, VD = +10V 25 Full 25 25 Full -15 -0.5 -5 40 - 15 100 125 15 0.5 5 V nA nA 4 DG408, DG409 Electrical Specifications PARAMETER Drain OFF Leakage Current, ID(OFF) DG408 Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) TEST CONDITIONS VEN = 0V, VD = 10V, VS = +10V TEMP (oC) 25 Full DG409 VS = VD = 10V (Note 7) 25 Full DG409 25 Full POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IPositive Supply Current, I+ VEN = 2.4V, VA = 0V (Enabled) VEN = 0V, VA = 0V (Standby) Full Full 25 Full Full -75 -500 10 1 0.2 75 0.5 2 A A mA mA A -1 -20 -1 -10 1 20 1 10 nA nA nA nA 25 Full Drain ON Leakage Current, ID(ON) DG408 (NOTE 5) MIN -1 -20 -1 -10 (NOTE 6) TYP (NOTE 5) MAX 1 20 1 10 UNITS nA nA nA nA Negative Supply Current, I- Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified TEST CONDITION TEMP (oC) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANS Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q VS1 = 8V, VS8 = 0V, VIN = 2.4V VINH = 2.4V, VINL = 0V, VS1 = 5V CL = 10nF, VGEN = 0V, RGEN = 0 25 25 25 25 - 180 180 120 5 - ns ns ns pC ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON-Resistance, rDS(ON) NOTES: 5. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. 7. Sequence each switch ON. 8. rDS(ON) = rDS(ON) (Max) - rDS(ON) (Min). 9. Worst case isolation occurs on channel 4 due to proximity to the drain pin. VD = 3V, 10V, IS = -1mA (Note 7) Full 25 0 90 12 V 5 DG408, DG409 Test Circuits and Waveforms +15V +2.4V EN A0 LOGIC INPUT 50 A1 A2 V+ S1 8 +15V +2.4V 10V 10V SWITCH OUTPUT VO 35pF LOGIC INPUT 50 EN V+ S1B 10V 10V SWITCH OUTPUT VO 35pF S2 - S7 DG408 S GND VD S1A - S4A, DA A0 DG409 S4B A1 GND VDB 300 300 -15V FIGURE 1A. DG408 TEST CIRCUIT -15V FIGURE 1B. DG409 TEST CIRCUIT LOGIC INPUT 3V 50% 0V VS1 S1 ON 50% tr < 20ns tf < 20ns SWITCH OUTPUT VO 0.8 VS1 0.8 VS8 tTRANS S8 ON tTRANS 0V VS8 FIGURE 1C. MEASUREMENT POINTS FIGURE 1. TRANSITION TIME +15V +15V A0 LOGIC INPUT A1 VIN 50 A2 V+ S1 DG408 S2 - S8 VD -5V SWITCH OUTPUT VO 300 35pF LOGIC INPUT VIN 50 EN GND V+ S1B DG409 A1 S1A - S4A S2B - S4B, DA EN GND V- DB A0 -5V SWITCH OUTPUT Vo 300 35pF -15V FIGURE 2A. DG408 TEST CIRCUIT -15V FIGURE 2B. DG409 TEST CIRCUIT LOGIC INPUT VIN 3V 50% 0V tON(EN) 0V 50% tr < 20ns tf < 20ns SWITCH OUTPUT VO VO 0.9 VO tOFF(EN) FIGURE 2C. MEASUREMENT POINTS FIGURE 2. ENABLE SWITCHING TIMES 6 DG408, DG409 Test Circuits and Waveforms +15V +2.4V V+ EN ALL S AND DA A0 LOGIC INPUT 50 A1 A2 DG408 DG409 GND VD, DB 300 +5V (VS) VS SWITCH OUTPUT VO 35pF SWITCH OUTPUT VO 0V tOPEN 80% 80% LOGIC INPUT 3V 0V (Continued) tr < 20ns tf < 20ns -15V FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE INTERVAL +15V LOGIC INPUT D CL 10nF VO SWITCH OUTPUT VO 3V 0V RGEN SX VGEN CHANNEL SELECT A0 A1 A2 EN GND V+ ON OFF VVO IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER ERROR, Q Q = CL x VO LOGIC INPUT -15V FIGURE 4A. TEST CIRCUIT FIGURE 4. CHARGE INJECTION FIGURE 4B. MEASUREMENT POINTS 0V +15V VIN SX | | S8 A2 SIGNAL GENERATOR A1 A0 GND VEN V+ 1k VO D 1k SIGNAL GENERATOR VIN 5V +15V S1 SX | | S8 A2 A1 A0 EN V+ VO D 1k VGND -15V ANALYZER V OUT OFF ISOLATION = 20 Log ----------------V IN ANALYZER -15V V OUT CROSSTALK = 20 Log ----------------V IN FIGURE 5. OFF ISOLATION FIGURE 6. CROSSTALK 7 DG408, DG409 Test Circuits and Waveforms 5V +15V VIN S1 EN V+ A2 VO D SIGNAL GENERATOR A2 A1 A0 GND VGND RL A0 VD CHANNEL SELECT A1 EN V+ S1 | | S8 IMPEDANCE ANALYZER (Continued) 3V OR 0V +15V -15V ANALYZER V OUT INSERTION LOSS = 20 Log ----------------V IN -15V FIGURE 7. INSERTION LOSS FIGURE 8. SOURCE/DRAIN CAPACITANCES Typical Applications Overvoltage Protection A very convenient form of overvoltage protection consists of adding two small signal diodes (1N4148, 1N914 type) in series with the supply pins (see Figure 9). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal V+ or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference V+ - (V-) doesn't exceed 44V. The addition of these diodes will reduce the analog signal range to 1V below V+ and 1V above V-, but it preserves the low channel resistance and low leakage characteristics. Typical application information is for Design Aid Only, not guaranteed and not subject to production testing. V+ 1N4148 SX D DG408 VG 1N4148 V- FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING DIODES 8 DG408, DG409 Typical Performance Curves 3.5 3.0 V+ = +15V V- = -15V 2.0 CS, D (pF) IIN (pA) 50 CD(OFF) 75 CD(ON) 1.0 0.5pA 0.0 25 CS(OFF) -1.0 0 5 VIN (V) 10 15 0 0 4 VA (V) 8 12 FIGURE 10. INPUT LOGIC CURRENT vs LOGIC INPUT VOLTAGE 80 V+ = +15V V- = -15V 60 CD(ON) FIGURE 11. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) VSUPPLY = 15V VIN = 0V 0 CS, D (pF) -200 40 IIN (pA) -400 20 -600 15 -800 -55 5 45 TEMPERATURE (oC) 85 125 CD(OFF) CS(OFF) 0 -15 0 VA (V) FIGURE 12. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE 60 DG408 ID(OFF) DG409 ID(OFF) 20 ID (pA) DG409 ID(ON) DG408 ID(ON) FIGURE 13. LOGIC INPUT CURRENT vs TEMPERATURE 100 V+ = 15V V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON) 40 60 20 ID (pA) 0 -20 -20 VS = 0V FOR ID(OFF) VS = VD FOR ID(ON) 0 2 4 6 VD (V) 8 10 12 -60 DG409 ID(OFF) -40 -60 -100 DG409 ID(ON) DG408 ID(ON), ID(OFF) -140 -15 0 VS , VD (V) 15 FIGURE 14. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN VOLTAGE (SINGLE 12V SUPPLY) FIGURE 15. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN VOLTAGE 9 DG408, DG409 Typical Performance Curves 20 (Continued) 2.0 15 1.5 10 IS(OFF) (pA) V+ = +15V V- = -15V VIN (V) V+ = +12V V- = 0V 1.0 5 0 0.5 -5 0.0 -15 0 VS (V) 15 4 8 12 VSUPPLY (V) 16 20 -10 FIGURE 16. SOURCE LEAKAGE CURRENT vs SOURCE VOLTAGE 105 VSUPPLY = 15V 104 103 -(I-) (A) 102 10 EN = 0V EN = 2.4V FIGURE 17. INPUT SWITCHING THRESHOLD vs SUPPLY VOLTAGE 104 VSUPPLY = 15V 103 102 I+ (mA) 10 1 0.1 EN = 2.4V 1 EN = 0V 0.1 100 1K 10K 100K 1M 10M SWITCHING FREQUENCY (Hz) 0.01 100 1K 10K 100K 1M 10M SWITCHING FREQUENCY (Hz) FIGURE 18. NEGATIVE SUPPLY CURRENT vs SWITCHING FREQUENCY 105 104 103 I+, I- (nA) 102 10 1 FIGURE 19. POSITIVE SUPPLY CURRENT vs SWITCHING FREQUENCY VSUPPLY = 15V I+ 0 -200 I- (nA) -400 V+ = 15V V- = -15V VIN = 0V VEN = 0V -600 0.1 0.01 -55 5 45 85 125 TEMPERATURE (oC) -(I-) -800 -55 45 5 TEMPERATURE (oC) 85 125 FIGURE 20. ISUPPLY vs TEMPERATURE FIGURE 21. NEGATIVE SUPPLY CURRENT vs TEMPERATURE 10 DG408, DG409 Typical Performance Curves 20 (Continued) 90 V+ = 15V V- = -15V VIN = 0V VEN = 0V Q (pC) 80 70 60 50 V+ = 15V V- = -15V CL = 10,000pF VIN = 5VP-P 15 I+ (A) 40 30 20 10 5 10 0 V+ = 12V V- = 0V -15 -10 -5 0 VS (V) 5 10 15 0 -55 -10 5 45 85 125 TEMPERATURE (oC) FIGURE 22. POSITIVE SUPPLY CURRENT vs TEMPERATURE (DG408) 120 FIGURE 23. CHARGE INJECTION vs ANALOG VOLTAGE 160 140 100 5V 80 rDS(ON) () 8V 60 10V 12V rDS(ON) () 100 80 60 40 20 15V 20 20V 0 -20 -16 -12 -8 -4 0 VD (V) 4 8 12 16 20 0 0 4 V- = 0V 120 V+ = 7.5V 10V 12V 15V 20V 22V 40 8 12 VD (V) 16 20 22 FIGURE 24. rDS(ON) vs VD AND SUPPLY 80 70 60 125oC rDS(ON) () 85oC 25oC rDS(ON) () 50 40 30 20 10 0 -15 0 VS (V) 15 0oC -40oC -55oC 30 90 V+ = 15V V- = -15V 130 FIGURE 25. rDS(ON) vs VD (SINGLE SUPPLY) 125oC 110 85oC 25oC 70 50 0oC -40oC -55oC 0 4 VS (V) 8 V+ = 12V V- = 0V 12 10 FIGURE 26. rDS(ON) vs VS AND TEMPERATURE FIGURE 27. rDS(ON) vs VS AND TEMPERATURE (SINGLE SUPPLY) 11 DG408, DG409 Typical Performance Curves -150 V+ = +15V V- = -15V RL = 1k (Continued) 275 250 225 -130 -110 t (ns) (dB) OFF ISOLATION 200 175 -90 tTRANS -70 150 -50 -30 100 CROSSTALK 125 100 1K 10K 100K 1M 10M 100M 8 9 10 11 12 tON(EN) tOFF(EN) 13 14 15 FREQUENCY (Hz) VSUPPLY (V) FIGURE 28. OFF ISOLATION AND CROSSTALK vs FREQUENCY FIGURE 29. SWITCHING TIME vs SINGLE SUPPLY 200 tTRANS 175 190 tTRANS 170 150 t (ns) t (ns) 150 tON(EN) 125 tOFF(EN) 100 tON(EN) 75 10 130 110 tOFF(EN) 90 12 14 16 VSUPPLY (V) 18 20 22 2 3 VIN (V) 4 5 FIGURE 30. SWITCHING TIME vs BIPOLAR SUPPLY FIGURE 31. SWITCHING TIME vs VIN (SINGLE SUPPLY) 180 tTRANS 160 1 0 -1 LOSS (dB) RL = 1k 140 t (ns) -2 -3 -4 -5 V+ = +15V V- = -15V REF. 1VRMS 120 tOFF(EN) 100 tON(EN) 80 2 3 VIN (V) 4 5 RL = 50 -6 10 102 103 104 105 106 FREQUENCY (Hz) 107 108 FIGURE 32. SWITCHING TIME vs VIN (BIPOLAR SUPPLY) FIGURE 33. INSERTION LOSS vs FREQUENCY Die Characteristics 12 DG408, DG409 DIE DIMENSIONS: 1800m x 3320m x 485m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG408 EN (2) A0 (1) A1 (16) A2 (15) GND (14) NC V- (3) (13) V+ S1 (4) (12) S5 S2 (5) (11) S6 S3 (6) NC S4 (7) (8) D (9) S8 (10) S7 13 DG408, DG409 Die Characteristics DIE DIMENSIONS: 1800m x 3320m x 485m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG409 EN (2) A0 (1) A1 (16) GND (15) NC NC V- (3) (14) V+ S1A (4) (13) S1B S2A (5) (12) S2B S3A (6) (11) S3B S4A (7) (8) DA (9) DB (10) S4B 14 DG408, DG409 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 15 DG408, DG409 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C AM BS 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 16 |
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